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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Paperback Engels 2018 9789811093210
Verwachte levertijd ongeveer 9 werkdagen

Samenvatting

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. 

Specificaties

ISBN13:9789811093210
Taal:Engels
Bindwijze:paperback
Uitgever:Springer Nature Singapore

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Inhoudsopgave

<br>Introduction.- Background.- Related Work.- High-level Fault Injection and Simulation.- Architectural Reliability Estimation.- Architectural Reliability Exploration.- System-level Reliability Exploration.- Conclusion and Outlook.<br>

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        High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip